IBRS and IBPB supported : yes STIBP supported : yes Spec arch caps supported : yes Number of physical cores: 32 Number of logical cores: 64 Number of online logical cores: 64 Threads (logical cores) per physical core: 2 Num sockets: 2 Physical cores per socket: 16 Core PMU (perfmon) version: 4 Number of core PMU generic (programmable) counters: 4 Width of generic (programmable) counters: 48 bits Number of core PMU fixed counters: 3 Width of fixed counters: 48 bits Nominal core frequency: 2300000000 Hz IBRS enabled in the kernel : no STIBP enabled in the kernel : no The processor is not susceptible to Rogue Data Cache Load: yes The processor supports enhanced IBRS : yes Package thermal spec power: 125 Watt; Package minimum power: 68 Watt; Package maximum power: 307 Watt; Socket 0: 2 memory controllers detected with total number of 6 channels. 3 QPI ports detected. 2 M2M (mesh to memory) blocks detected. 0 Home Agents detected. 3 M3UPI blocks detected. Socket 1: 2 memory controllers detected with total number of 6 channels. 3 QPI ports detected. 2 M2M (mesh to memory) blocks detected. 0 Home Agents detected. 3 M3UPI blocks detected. Delay: 20 Disabling NMI watchdog since it consumes one hw-PMU counter. Trying to use Linux perf events... Successfully programmed on-core PMU using Linux perf Link 3 is disabled Link 3 is disabled Socket 0 Max QPI link 0 speed: 23.3 GBytes/second (10.4 GT/second) Max QPI link 1 speed: 23.3 GBytes/second (10.4 GT/second) Socket 1 Max QPI link 0 speed: 23.3 GBytes/second (10.4 GT/second) Max QPI link 1 speed: 23.3 GBytes/second (10.4 GT/second)
EXEC : instructions per nominal CPU cycle IPC : instructions per CPU cycle FREQ : relation to nominal CPU frequency='unhalted clock ticks'/'invariant timer ticks' (includes Intel Turbo Boost) AFREQ : relation to nominal CPU frequency while in active state (not in power-saving C state)='unhalted clock ticks'/'invariant timer ticks while in C0-state' (includes Intel Turbo Boost) L3MISS: L3 (read) cache misses L2MISS: L2 (read) cache misses (including other core's L2 cache *hits*) L3HIT : L3 (read) cache hit ratio (0.00-1.00) L2HIT : L2 cache hit ratio (0.00-1.00) L3MPI : number of L3 (read) cache misses per instruction L2MPI : number of L2 (read) cache misses per instruction READ : bytes read from main memory controller (in GBytes) WRITE : bytes written to main memory controller (in GBytes) LOCAL : ratio of local memory requests to memory controller in % LLCRDMISSLAT: average latency of last level cache miss for reads and prefetches (in ns) PMM RD : bytes read from PMM memory (in GBytes) PMM WR : bytes written to PMM memory (in GBytes) L3OCC : L3 occupancy (in KBytes) TEMP : Temperature reading in 1 degree Celsius relative to the TjMax temperature (thermal headroom): 0 corresponds to the max temperature energy: Energy in Joules