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emmc的HS200特性

emmc设备支持的时钟模式:

Speed Modeclock (MHz)
Default Speed26
Hight Speed SDR52
Hight Speed DDR52
HS200200
HS400200

SDR : 单边沿采样
DDR : 双边沿采样

Hardware System

emmc hardware

DS(Data Strobe):This signal is generated by the device and used for data output and CRC status
response output in HS400 mode.

emmc gpio

注: 在电路的设计中需要将RST_n的pin脚可以控制,否则在第一次写数据是容易出现超时错误,因此可以通过mmc驱动控制软件控制,也可以通过硬件的系统reset时控制

Boot的状态转换

emmc boot

  1. GO_PRE_IDLE_STATE command (CMD0 with argument of 0xF0F0F0F0) is the software reset command and puts the device into Pre-idle State.
  2. Hardware reset may be used by host resetting a device , moving the device to Pre-idle state and disabling power-on period write protect on blocks that had been set as power-on write protect before the reset was asserted.

BOOT_PARTITION_ENABLE配置:

Extended CSD register进行设置,BOOT_PARTITION_ENABLE默认配置为0,(0x0 : Device not boot enabled (default))

Bus Speed Mode

emmc bus speed

HS200 Bus Speed Mode

The HS200 mode offers the following features:

  • SDR Data sampling method
  • CLK frequency up to 200MHz Data rate – up to 200MB/s
  • 4 or 8-bits bus width supported
  • Single ended signaling with 4 Drive Strengths
  • Signaling levels of 1.8V and 1.2V
  • Tuning concept for Read Operations

HS200 System Block Diagram

emmc hs200 block

After power-on or software reset(CMD0), the interface timing of the device is set as the default “Backward Compatible Timing “. Device shall select HS200 Timing mode if required and perform the Tuning process if needed.

HS200 Adjustable Sampling Host

The Host may use adjustable sampling to determine the correct sampling point. A predefined tuning block stored in Device may be used by the Host as an aid for finding the optimal data sampling point. The Host can use CMD21 tuning command to read the tuning block.

  1. HS200为什么需要tuning, 其作用,好处?

  2. 何时发生tuning,tuning的原理?

HS400 Bus Speed Mode

The HS400 mode has the following features:

  • DDR Data sampling method
  • CLK frequency up to 200MHz, Data rate is up to 400MB/s
  • Only 8-bit bus width supported
  • Signaling levels of 1.8V and 1.2V
  • Support up to 5 Drive Strengths
  • Data strobe signal is toggled only for Data out and CRC response

e•MMC device in HS400 mode while enabling Enhanced Strobe without the need for tuning procedure.

HS400 System Block Diagram

emmc hs400 block

For read operations, Data Strobe is generated by device output circuit. Host receives the data which is aligned to the edge of Data Strobe.

  1. DS信号初始状态啥样、何时、什么情况下发生跳变?

    • DS的初始信号为O/PP, 上拉高电平
      *
  2. HOST端接受数据为啥要与DS的边沿对齐?

  3. 为啥只支持8bit

  4. 为啥不需要和HS200 mode一样使用tuning?

  5. DStuning?

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  • 本文作者: Winddoing
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